This invention relates to a method of manufacturing a semiconductor device, which method comprises providing a semiconductor body having a first region of one conductivity type adjacent one major surface, providing an insulating layer on the one major surface, using masking means to form windows in the insulating layer over first and second areas of the one major surface, introducing impurities to form a relatively highly doped region of the opposite conductivity type adjacent the first area and a relatively lowly doped region of the opposite conductivity type adjacent the second area, and then introducing impurities of the one conductivity type for forming a region of the one conductivity type within the relatively lowly doped region of the opposite conductivity type.
Such a method is described in, for example, U.S. Pat. No. 4,485,552 which is concerned with the manufacture of complementary bipolar transistors within a single semiconductor body. As described in U.S. Pat. No. 4,485,552 the semiconductor body is a silicon body of one conductivity type, p conductivity type in the example, onto which the insulating layer is thermally grown as a silicon oxide layer of about 350 nm thickness. A first masking layer is used to define a window in the insulating layer over the second area into which, after formation of a thin protective oxide layer, phosphorus ions are implanted with a high energy and low dose for forming the relatively lowly doped region which will later form a barrier region for the pnp bipolar transistor.
A second masking layer is then used to define a window in the oxide layer over the first area and arsenic ions are then implanted to form, adjacent the first area, the relatively highly doped region of the opposite (n in this example) conductivity type which later serves as a buried part of the collector region of the npn bipolar transistor. A further thermal re-oxidation process is then carried out to close the window over the first area and a third masking layer is then used to enable windows to be opened for allowing the introduction of boron ions to form, as shown in FIG. 3 of U.S. Pat. No. 4,485,552, "cut-off" regions of the one conductivity type and at the same time to form through a window opened over the second area the region of the one conductivity type which later will form a buried part of the collector region of the pnp bipolar transistor. The insulating layer is then removed and a layer of, in the example described, epitaxial material of opposite conductivity type to the semiconductor body is grown on the one major surface. Recessed oxide isolation regions are then formed in the epitaxial layer to separate the areas of the respective bipolar transistors and further processing steps carried out to define an npn bipolar transistor at the first area and a pnp bipolar transistor at the second area.
Thus, in the method described in U.S. Pat. No. 4,485,552 three different implantation steps are carried out to form the buried parts of the collector regions of the complementary bipolar transistors and the isolation or barrier region for the pnp bipolar transistor and each of these implantation steps requires a separate masking layer to enable the necessary windows in the insulating layer to be opened.